• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    The invention relates to a memory cell formed in a wafer comprising a semiconductor substrate (SUB) covered with a first insulating layer (IL), the insulating layer being covered with an active layer (AL) made of a semiconductor material. , the memory cell comprising a selection transistor (ST) having a control gate (GT) and a first conduction terminal (DDP) connected to a variable resistance element (VZ), the gate (GT) being formed on the layer active and having a sidewall covered with a second insulating layer (SP), the variable resistance element (VZ) being formed by a layer (MO) of a variable resistance material deposited on a sidewall of the active layer in a first trench (TR) formed through the active layer along the lateral side of the grid, a conductive trench (BC) being formed in the first trench against a lateral flank of the resistive material layer; variable stance.
    公开号:FR3038132A1
    申请号:FR1555732
    申请日:2015-06-23
    公开日:2016-12-30
    发明作者:Philippe Boivin；Simon Jeannot
    申请人:STMicroelectronics Crolles 2 SAS；STMicroelectronics Rousset SAS；
    IPC主号:
    专利说明:

    [0001] The present invention relates to resistive memories, and more generally to memories in which each memory cell comprises a selection gate and a variable impedance element that can have several different states detectable by an impedance measurement.
    [0002] Depending on whether the element can maintain its state with or without power supply, the memory is volatile or nonvolatile. Thus, several types of resistive memories are under development. In the conductive-bridging random access memory (CBRAM) memories, the variable impedance element comprises two electrodes and a solid electrolyte thin layer disposed between the electrodes. Under the effect of polarization of the element, metal ions migrate from one of the two electrodes and the electrolyte to the other electrode, and form one or more filaments which reduce the electrical resistance of the element. The RRAM or Resistive RAM memories comprise a dielectric element which can be forced to be reversibly conductive by the formation of conductive filaments obtained by the application of a sufficiently high voltage. In particular, OxRAM memories use metal oxides (Ox) as a material whose resistance can be controlled in a reversible manner.
    [0003] In FeRAM or FRAM memories (Ferroelectric RAM), the variable resistance element comprises a capacitor whose dielectric is a ferroelectric material in which magnetic dipoles can be oriented along the field lines of an electric field formed between the electrodes when the capacitor is charged. When the capacitor is discharged, the dipoles retain their orientation. The variable resistance element of the MRAMs (Magnetoresistive RAM) comprises two plates of ferromagnetic material capable of producing an electric field, separated by a dielectric film. One of the plates is a permanent magnet, while the other plate generates a magnetic field that can be modified by an electric current. The state of the memory cell is read by a resistance measurement.
    [0004] FIGS. 1A, 1B schematically represent in section a semiconductor substrate SUB on which a memory cell MC is formed comprising a variable resistance element VZ. Figure 1A is a longitudinal sectional view along the AA 'plane shown in Figure 1B, and Figure 1B is a cross-sectional view along the BB' plane shown in Figure 1A. The memory cell MC comprises a selection transistor comprising a gate GT, DDP drain regions and SDP source on either side of the gate GT, and a channel region under the gate GT between the drain regions DDP and SDP source. The gate GT is made in a polycrystalline silicon layer formed on an insulating layer GO deposited on the substrate SUB. The DDP, SDP regions are formed by implanting dopants into the SUB substrate on either side of the GT gate. The memory cell MC is covered by a dielectric insulating material D1. The SDP source region is connected to a source line SL via a via via the insulating layer D1. The gate GT forms a word line WL extending parallel to the source line SL. The variable resistance element VZ is formed in the insulating layer D1 and is connected to the drain region DDP via a via formed in the insulating layer D1. The variable resistance element VZ is connected to a line 20 of bit BL formed on the surface of the insulating layer D1 via a via BC formed in the insulating layer D1. The bit line BL is perpendicular to the word lines WL and source SL. The memory cell is isolated from adjacent memory cells (or other circuit elements formed on the SUB substrate) by shallow isolation trenches STI1 parallel to the gate GT, and shallow insulation trenches STI2 perpendicular to the GT grid. The isolation trenches STI1 may be replaced by transistor gates, such as the gate GT, biased so as to keep the associated transistor in the off state. FIG. 2 shows the electrical circuit of a portion of a memory plane including memory cells such as the memory cell MC shown in FIGS. 1A, 1B. The memory plane comprises word lines WL, source lines SL parallel to the word lines WL and bit word lines perpendicular to the word lines WL and the source lines BL. Each memory cell MC comprises a selection transistor ST comprising a conduction terminal (source or drain) connected to a terminal of a variable resistance element VZ whose other terminal is connected to one of the bit lines BL. . The other conduction terminal of the selection transistor ST is connected to one of the source lines SL, and the gate terminal of the transistor ST is connected to one of the word lines WL.
    [0005] In order to reduce the area occupied by each memory cell, it has been proposed to make the memory cells in pairs, sharing a same conduction region connected to a source line SL, as in Fig. 2. In this embodiment, the The isolation trench ST1 on the left in FIG. 1A is replaced by a gate such as the gate GT to form the gate of the selection transistor of the other memory cell of the pair of memory cells. It is desirable to further reduce the occupied substrate area by a memory cell comprising a variable resistance element. Embodiments provide a memory cell comprising a selection transistor having a control gate and a first conduction terminal connected to a variable resistance element, the memory cell being formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer of a semiconductor material, the gate being formed on the active layer and having a sidewall covered with a second insulating layer, the variable resistance element being formed by a layer of variable resistance material, deposited on a sidewall of the active layer in a first trench formed through the active layer along the sidewall of the grid and reaching the first insulating layer, a trench conductor being formed in the first trench against a lateral flank of the layer of material variable resistance. According to one embodiment, the conductive trench is formed between two adjacent insulating trenches that it reaches, the two insulating trenches and the conducting trench delimiting between them the memory cell. According to one embodiment, the conductive trench passes through the two adjacent insulating trenches delimiting the memory cell. According to one embodiment, the layer of variable resistance material covers a portion of the bottom of the first trench, the conductive trench being formed in a second trench formed through the layer of variable resistance material. According to one embodiment, the entire substrate, the active layer and the first insulating layer form an FDSOI-type substrate.
    [0006] Embodiments may also relate to a memory comprising at least two memory cells as previously defined, the control gate of each memory cell being connected to a word line of the memory, the variable resistance element of each memory cell. being connected to a bit line of the memory, the selection transistor 10 of each memory cell including a second conduction terminal connected to a source line of the memory. According to one embodiment, the variable resistance elements of the two memory cells are formed in the first trench and are separated from each other by the conductive trench connected to the same bit line. According to one embodiment, the conductive trench is in direct contact with other variable resistance elements of other memory cells of the memory, and forms the bit line. According to one embodiment, the second conduction terminal of each memory cell is shared with another memory cell of the memory. Embodiments may also relate to a method of manufacturing an integrated circuit comprising a memory cell, the method comprising the steps of: forming a selection transistor on a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor material, the selection transistor comprising a control gate and first and second conduction terminals, covering with a second insulating layer a lateral flank of the control gate of the next to the first conduction terminal, making a trench through the active layer in the first conduction terminal, reaching the first insulating layer, depositing a layer of variable resistance material, in the first trench, covering a lateral flank of the active layer in the first trench, and forming in the layer 35 a conductive trench reaching the first insulating layer.
    [0007] According to one embodiment, the conductive trench is made by etching a second trench in the layer of variable resistance material through a mask, and filling the second trench with a conductive material.
    [0008] According to one embodiment, the conductive trench is formed by applying an anisotropic etching to the layer of variable resistance material until it reaches the first insulating layer at the bottom of the first trench and filling the first trench with a trench. conductive material.
    [0009] According to one embodiment, the conductive trench is formed to separate the layer of variable resistance material at the bottom of the first trench into two portions respectively forming two variable resistance members of two memory cells sharing the conductive trench to connect the trenches. two memory cells at one bit line.
    [0010] Exemplary embodiments of the invention will be described in the following, in a nonlimiting manner in relation to the appended figures in which: FIGS. 1A, 1B, previously described, show schematically in transverse and longitudinal sections, a semiconductor substrate in which is formed a conventional memory cell comprising a variable resistance element, Figure 2 described above, schematically shows the electrical circuit of a memory array comprising variable resistance element memory cells, such as that of Figures 1A, 1B, 25 FIGS. 3A, 3B and 3C show schematically a semiconductor substrate in which memory cells comprising a variable resistance element are formed, according to one embodiment, respectively in cross-section, in longitudinal section and in plan view, FIG. 4 schematically represents the electrical circuit of a plane memory comprising variable resistance element memory cells, such as that of FIG. 3A, FIG. 5 is a top view of memory cells, according to another embodiment, FIG. 6 schematically represents the electrical circuit of FIG. a memory array comprising variable resistance element memory cells, such as those of FIG. 5; FIGS. 7A to 7E show schematically in cross-section a semiconductor substrate at different stages of fabrication of a memory cell such as that In FIG. 3A, according to one embodiment, FIGS. 8A and 8B show in cross-section a semiconductor substrate at different stages of fabrication of a memory cell, according to another embodiment. FIGS. 3A, 3B, 3C schematically represent a semiconductor substrate SUB on which is formed a memory cell MC1, comprising a variable resistance element VZ, according to one embodiment. Fig. 3A is a sectional view along the AA 'plane shown in Fig. 3B, and Fig. 3B is a sectional view along the BB' plane shown in Fig. 3A. The substrate SUB is silicon on insulator type SOI (Silicon on Insulator) and comprises an insulating layer IL formed on one side of the SUB substrate and an active layer AL in a semiconductor material, for example made of silicon, formed on the insulating layer HE. The SUB substrate may be of FDSOI (Fully Depleted SOI) type. The memory cell MC1 comprises a selection transistor comprising a gate GT formed on the substrate SUB, and conduction regions SDP and DDP respectively formed on both sides of the gate GT. The gate GT is formed of a conductive material such as doped polycrystalline silicon, on an insulating layer GO, for example oxide SiO 2, deposited on the active layer AL. The GT grid forms a channel region between the DDP and SDP regions. The SDP and DDP regions are produced by implantation of dopants in the active layer AL. The SDP region thus forms a conduction region common to the selection transistors of the memory cell MC and an adjacent memory cell. A via is formed on the SDP region to connect the latter to a source line SL. The grid GT and in particular the lateral flanks of the grid, are covered with a dielectric layer SP forming a spacer. The memory cell MC1 is covered by a dielectric insulating material D1 which may also be SiO2 oxide or a metal oxide. In FIGS. 3B and 3C, adjacent memory cells are isolated from each other by adjacent STI2 isolation trenches formed in the active layer AL and reaching the insulating layer IL. According to one embodiment, a first trench is made between the spacers SP of the gate GT and an adjacent gate GT1, through the active layer AL in the region DDP, until reaching the insulating layer IL. A layer of a variable resistance material is deposited and etched so as to partially cover an insulating layer deposited on grids GT, GT1, SP spacers and the substrate region 10 between spacers SP grids GT, GT1, and in particular lateral flanks of the active layer AL in the first trench. A second trench is formed in the center of the first trench in the layer of variable resistance material. The second trench thus forms two elements with variable resistance VZ. The second trench is filled with a conductive material so as to form a conductive trench BC between the memory cells. The conducting trench BC thus forms a bit line BL. In this manner, the layer of variable resistance material forms a variable resistance element VZ, for both the memory cell MC1 and the adjacent memory cell having the gate GT1.
    [0011] The variable resistance layer VZ may be a solid electrolyte or a dielectric material capable of forming filaments under the effect of a voltage applied between the electrodes, or a ferromagnetic material, or a material capable of taking amorphous and crystalline. The variable resistance layer VZ may be made of a metal oxide such as copper oxide (CuO), silicon oxide (SiO2), hafnium oxide (HfO2), nickel oxide ( NiO), zinc oxide (ZnO), aluminum oxide or alumina (Al 2 O 3), vanadium oxide (VO 2) or strontium titanate oxide (SrTiO 3). The memory cell structure which has just been described makes it possible to offer a relatively large substrate area gain by virtue of the fact that the spaces between the grids GT, GT1 are shared by two adjacent memory cells. With respect to the structure shown in FIGS. 1A, 1B, the memory cell structure shown in FIGS. 3A-3C reduces by approximately 29% the length of the substrate occupied by a memory cell, while maintaining the dimensions of the memory cells. elements constituting the memory cells. FIG. 4 is an electrical diagram of a memory plane MA1 comprising several memory cells, such as the memory cell MC1.
    [0012] The memory array includes bit lines BL, word lines WL parallel to bit lines BL, and source lines SL perpendicular to bit lines BL and word lines WL. Each memory cell MC1 comprises a selection transistor ST, and a variable resistance element VZ such as that represented in FIGS. 3A, 3B. The transistor ST has a conduction terminal (source or drain) connected to a terminal of the variable resistance element VZ whose other terminal is connected to one of the bit lines BL. The other conduction terminal (drain or source) of the selection transistor ST is connected to one of the source lines SL. The transistor ST has a gate terminal connected to one of the word lines WL. The resistance of the element VZ can be changed between a highly resistant state and a weakly resistant state by applying to it a voltage greater than a threshold voltage (unipolar memories) or an inverted voltage (bipolar memories). It should be noted that the conduction regions DDP, SDP of the selection transistor ST can form indifferently a drain terminal and a source terminal of the transistor, and that the functions of the bit lines BL and source SL can be inverted. Thus, in FIG. 5 represents memory cells MC2 which differ from the memory cells MC1 in that the conducting trench BC 25 forming the bit line BL is interrupted above the trenches STI2, so as to form sections separating segments of the active layer AL, the sections of the active layer AL being delimited by two adjacent trenches STI2. It should be noted that by providing sections BC completely separating two aligned portions of active layer AL between two grids GT, it avoids the formation of parasitic resistances between the two aligned sections of the active layer AL. FIG. 6 is a circuit diagram of a memory plane MA2 comprising a plurality of memory cells, such as the memory cell MC2 of FIG. 5. The memory plane MA2, which is equivalent to the memory plane MA1 (FIG. 4), differs from the latter. simply that the bit lines BL 3038132 9 are perpendicular to the word lines WL and the source lines SL. It should be noted that the structure of the memory cell MC2 can be used both in the memory plane MA2 and in the memory plane MA1 (FIG. 4). Figs. 7A to 7E show a portion of the SUB substrate on which several memory cells of the MA1 or MA2 memory array are formed. FIG. 7A shows the substrate after the realization of GT grids and SP spacers formed on grids GT. During a manufacturing step illustrated in FIG. 7A, trenches TR are formed in the active layer AL between the spacers SP formed on the grids GT, the trenches TR 10 being made so as to reach the insulating layer IL. At subsequent manufacturing steps, illustrated in FIG. 7B, the substrate SUB is covered with a dielectric layer DL, including in trenches TR. The DL layer is for example made of a metal oxide.
    [0013] In the following manufacturing steps, illustrated in FIG. 7C, the insulating layer DL is etched so as to clear the trenches TR between the spacers SP covering the grids GT. The surface of the substrate and the trenches TR are then covered with a substantially uniform thickness layer MO of the material for forming the variable resistance elements VZ. In the following manufacturing steps, illustrated in FIG. 7D, the surface of the substrate is covered with a dielectric layer DL1, including in trenches TR1 covered with the layer MO. The layer DL1 is then etched through a mask so as to form trenches TR2 substantially in the center of the trenches TR, crossing the MO layer and reaching the insulating layer IL. At subsequent manufacturing steps, illustrated in FIG. 7E, the trenches TR2 are filled with a conductive material to form a conductive trench BC, and to form the variable resistance elements VZ in the MO layer, on both sides. another of each trench TR2. For example, the walls and the bottom of the trenches TR2 may be covered with a conductive layer, for example made of titanium or titanium nitride, and the trenches TR2 may then be filled with tungsten or copper. The DL, DL1 layers can be made of PMD (Polysilicon Metal Dielectric).
    [0014] The conductive trenches BC may directly form the bit lines BL as illustrated in FIG. 3C or be cut into sections as illustrated in FIG. 5. FIGS. 8A, 8B represent manufacturing steps that can be carried out as a result the step of etching the DL dielectric layer and depositing the MO layer (Figure 7C), according to another embodiment. FIG. 8A illustrates an anisotropic etching step of the MO layer, performed until the material of the MO layer at the bottom of the trenches TR is completely removed, and the insulating layer IL is discovered, as to form spacers on the lateral flanks of TR trenches. This step makes it possible to produce elements with variable resistance VZ on each side facing each trench TR between two grids GT, and for each section of active layer AL between two adjacent trenches STI2. At subsequent manufacturing steps, illustrated in FIG. 8B, the trenches TR between the variable resistor elements VZ are filled with a conductive material to form the conductive trench BC constituting a bit line BL. By realizing the variable resistance elements VZ by the spacer forming technique, the conductive trench BC is autocentered between two adjacent GT grids. Thus, it is ensured that the thicknesses d1, d2 of the variable resistance elements VZ between the active layer AL and the conductive trench BC are substantially identical, and therefore that the resistance values of the elements VZ are also substantially identical. The various embodiments of memory cells presented above can be performed on a FDSOI (Fully Depleted SOI) type substrate, with IL active and insulating layers IL respectively having thicknesses of the order of 7 nm and 25 nm. It will be apparent to those skilled in the art that the present invention is capable of various alternative embodiments and various applications.
    [0015] In particular, the invention is not limited to a memory, but also covers a single memory cell formed in an SOI type substrate. In this case in particular, it is not necessary to provide self-centering of the contact BC in the variable resistance material, since only one variable resistance element is to be produced.
    [0016] It should also be noted that the memory cell can be made on a conventional semiconductor substrate on which an insulating layer (IL) has been deposited, the semiconductor layer AL being formed on the insulating layer, for example by epitaxy. 5
    权利要求:
    Claims (13)
    [0001]
    REVENDICATIONS1. Memory cell comprising a selection transistor (ST) having a control gate (GT) and a first conduction terminal (DDP) connected to a variable resistance element (VZ), characterized in that it is formed in a wafer comprising a semiconductor substrate (SUB) covered with a first insulating layer (IL), the insulating layer being covered with an active layer (AL) in a semiconductor material, the gate (GT) being formed on the active layer and having a lateral flank covered by a second insulating layer (SP), the variable resistance element (VZ) being formed by a layer (MO) of a variable resistance material deposited on a lateral flank of the active layer in a first trench (TR) formed through the active layer along the sidewall of the grid and reaching the first insulating layer, a conductive trench (BC) being formed in the first trench against a lateral flank of the layer of variable resistance material.
    [0002]
    2. The memory cell of claim 1, wherein the conductive trench (BC) is formed between two adjacent insulating trenches (STI2) that it reaches, the two insulating trenches and the conducting trench delimiting between them the memory cell (MC1, MC2). ).
    [0003]
    3. The memory cell of claim 2, wherein the conductive trench (BC) passes through the two adjacent insulating trenches (STI2) delimiting the memory cell (MC1).
    [0004]
    A memory cell according to claim 3, wherein the layer of variable resistance material (MO) covers a portion of the bottom of the first trench (TR), the conductive trench (BC) being formed in a second trench formed through the layer of variable resistance material. 3038132 13
    [0005]
    5. Memory cell according to one of claims 1 to 4, wherein the entire substrate (SUB), the active layer (AL) and the first insulating layer (IL) forms a FDSOI type substrate. 5
    [0006]
    6. Memory comprising at least two memory cells (MC1, MC2) according to one of claims 1 to 5, the control gate (GT) of each memory cell being connected to a word line (WL) of the memory, variable resistance element (VZ) of each memory cell being connected to a bit line (BL) of the memory, the selection transistor (ST) of each memory cell comprising a second conduction terminal (SDP) connected to a source line (SL) of the memory.
    [0007]
    The memory of claim 6, wherein the variable resistance elements (VZ) of the two memory cells (MC1, MC2) are formed in the first trench (TR) and are separated from each other by the trench. conductive (BC) connected to the same bit line (BL).
    [0008]
    8. Memory according to one of claims 6 and 7, wherein the conductive trench (BC) is in direct contact with other variable resistance elements (VZ) of other memory cells of the memory, and forms the line. bit (BL).
    [0009]
    9. Memory according to one of claims 6 to 8, wherein the second conduction terminal (SDP) of each memory cell (MC1, MC2) is shared with another memory cell memory.
    [0010]
    A method of manufacturing an integrated circuit comprising a memory cell (MC1, MC2), the method comprising the steps of: forming a selection transistor (ST) on a semiconductor substrate (SUB) covered with a first insulating layer (IL), the insulating layer being covered with an active layer (AL) of a semiconductor material, the selection transistor comprising a control gate (GT) and first and second conduction terminals (DDP, SDP), cover with a second insulating layer (SP) a lateral flank of the control gate on the side of the first conduction terminal (DDP), 3038132 14 make a trench (TR) through the active layer in the first conduction terminal, reaching the first insulating layer, depositing a layer (MO) of a variable resistance material, in the first trench, covering a lateral flank of the active layer in the first trench, and forming in the mat layer Variable resistor wire a conductive trench (BC) reaching the first insulating layer.
    [0011]
    The method of claim 10, wherein the conductive trench (BC) is made by etching a second trench (TR2) in the layer of variable resistance material (MO) through a mask, and filling the second trench of a conductive material.
    [0012]
    The method of claim 10, wherein the conductive trench (BC) is formed by applying to the layer of variable resistance material (MO) an anisotropic etching, until reaching the first insulating layer (IL) at the bottom of the the first trench (TR), and filling the first trench with a conductive material. 20
    [0013]
    The method of claim 11 or 12, wherein the conductive trench (BC) is formed to separate the layer of variable resistance material (MO) at the bottom of the first trench (TR) into two parts respectively forming two elements. variable resistance (VZ) of two memory cells sharing the conductive trench to connect the two memory cells to a bit line (BL).
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    引用文献:
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    法律状态:
    2016-05-24| PLFP| Fee payment|Year of fee payment: 2 |
    2016-12-30| PLSC| Search report ready|Effective date: 20161230 |
    2017-05-23| PLFP| Fee payment|Year of fee payment: 3 |
    2018-05-25| PLFP| Fee payment|Year of fee payment: 4 |
    2019-05-22| PLFP| Fee payment|Year of fee payment: 5 |
    2020-05-20| PLFP| Fee payment|Year of fee payment: 6 |
    优先权:
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    FR1555732A|FR3038132B1|2015-06-23|2015-06-23|RESISTIVE MEMORY CELL HAVING A COMPACT STRUCTURE|FR1555732A| FR3038132B1|2015-06-23|2015-06-23|RESISTIVE MEMORY CELL HAVING A COMPACT STRUCTURE|
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